1. Field of the Invention
The present invention relates to a method for designing a semiconductor integrated circuit. More specifically, it relates to a method for designing a semiconductor integrated circuit by which variation in transistor properties is suppressed during exposure and etching by forming a dummy gate polysilicon pattern in a cell base IC.
2. Description of the Related Art
Recently, due to advances in fine pattern technology, transistor properties have been greatly affected by subtle changes in dimensions during manufacture. One of these effects has created a problem in that a gate length is varied due to a low or high density of the gate polysilicon during manufacture. This is due to the fact that the peripheral density of the gate polysilicon influences the proximity effect during exposure and the etching rate.
Although such variations in gate length has therefore been negligible because the gate length has been long relative to the variations, it has recently become impossible to ignore the variation due to a difference in the influence on the proximity effect during exposure and on the etching rate. Variation in the gate length causes variation in transistor properties, and thus clock skew is increased. An increase of clock skew requires many margins in design, thereby causing another problem in that this is disadvantageous for high-speed operation of a circuit.
As cited reference 1, FIG. 1 shows a method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-open No. 4-48715. The exposure is performed by the use of a normal pattern and reticle 306 of a dummy pattern formed in the periphery of the pattern shown in FIG. 1(a), whereby the normal pattern is uniformly influenced by the proximity effect and thus it is possible to suppress the variation in the gate length of a resist during the exposure. Next, the exposure is performed by the use of reticle 313 for removing the dummy pattern shown in FIG. 1(b), whereby the resist of the uniform gate length of the normal pattern alone can be developed as shown in FIG. 1(c).
As cited reference 2, FIG. 2 shows the semiconductor device disclosed in Japanese Patent Application Laid-open No. 6-295595. As shown in FIG. 2(a), it can be seen that, since storage device M1 is mounted in a peripheral circuit, the density is reduced in the periphery of storage device M1. Thus, as shown in FIG. 2(b), dummy cells Mll-Mnn are arranged in the periphery of storage device M1 to thereby prevent the gate polysilicon of storage device M1 from being reduced during the exposure and the etching. That is, the variation in the gate length of a main cell and storage device M1 is suppressed.
The above-described prior art have the following problems.
In cited reference 1, another reticle and another step are additionally required for removing the dummy pattern. Furthermore, although this method can suppress the variation in gate length of the resist during exposure, since an area of a low-density resist pattern is excessively etched during the etching, the gate length of the gate polysilicon is varied.
The cited reference 2 is not applicable in the following case, that is, when it is not previously known that the area in which the cell to be processed (storage device M1) is arranged has low density, or when it is not possible to ensure that the area in which all of n.sup.2 dummy cells Mll-Mnn are arranged in a matrix is located at the periphery of the cell to be processed. Moreover, when a cell to be processed has an intermediate density between low and high densities, the dummy cells are not arranged near the cell to be processed, and thus disadvantageous variations result.